View LM3310_9083688.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 LM3310 step-up pwm dc/dc converter with integrated op-amp and gate pulse modulation switch check for samples: LM3310 1 features description the LM3310 is a step-up dc/dc converter integrated 2 ? boost converter with a 2a, 0.18 ? switch with an operational amplifier and a gate pulse ? boost output voltage adjustable up to 20v modulation switch. the boost (step-up) converter is ? operating voltage range of 2.5v to 7v used to generate an adjustable output voltage and features a low r dson internal switch for maximum ? 660khz/1.28mhz pin selectable switching efficiency. the operating frequency is selectable frequency between 660khz and 1.28mhz allowing for the use of ? adjustable soft-start function small external components. an external soft-start pin ? input undervoltage protection enables the user to tailor the soft-start time to a specific application and limit the inrush current. the ? over temperature protection op-amp is capable of sourcing/sinking 135ma of ? integrated op-amp current (typical). the gate pulse modulation switch ? integrated gate pulse modulation (gpm) can operate with a vgh voltage of 5v to 30v. the switch LM3310 is available in a low profile 24-lead wqfn package. ? 24-lead wqfn package applications ? tft bias supplies ? portable applications typical application circuit 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2005 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. v dd c ss c in c out v in fb sw ss agnd pos neg shdn freq LM3310 v c d 3 d 2 d 1 v out l r fb1 r fb2 v in r c pgnd out vdpm vghm vflk ce re vgh r e c e av in c1 c2 r1 r2 c c v out = 2 x v oh
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com connection diagram top view figure 1. wqfn-24 package see package number rtw0024a ja =37 c/w pin descriptions pin name function 1 nc not internally connected. leave pin open. 2 vghm output of gpm circuit. this output directly drives the supply for the gate driver circuits. 3 vflk determines when the tft lcd is on or off. this is controlled by the timing controller in the lcd module. 4 vdpm vdpm pin is the enable signal for the gpm block. pulling this pin high enables the gpm while pulling this pin low disables it. vdpm is used for timing sequence control. 5 v dd reference input for gate pulse modulation (gpm) circuit. the voltage at v dd is used to set the lower vghm voltage. if the gpm function is not used connect v dd to v in . 6 av in op-amp analog power input. 7 out output of the op-amp. 8 neg negative input terminal of the op-amp. 9 pos positive input terminal of the op-amp. 10 agnd analog ground for the step-up regulator, ldo, and op-amp. connect directly to dap and pgnd beneath the device. 11 nc not internally connected. leave pin open. 12 nc not internally connected. leave pin open. 13 nc not internally connected. leave pin open. 14 ss boost converter soft start pin. 15 v c boost compensation network connection. connected to the output of the voltage error amplifier. 16 freq switching frequency select input. connect this pin to v in for 1.28mhz operation and agnd for 660khz operation. 17 v in boost converter and gpm power input. 18 sw boost power switch input. switch connected between sw pin and pgnd pin. 19 shdn shutdown pin. active low, pulling this pin low disable the LM3310. 20 fb boost output voltage feedback input. 21 pgnd power ground. source connection of the step-up regulator nmos switch and ground for the gpm circuit. connect agnd and pgnd directly to the dap beneath the device. 2 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310 nc vghm vflk neg vdpm pos agnd v dd nc av in out swv in v c 12 11 10 9 8 7 13 14 18 17 16 15 1 2 3 4 5 6 21 22 23 24 nc ss nc freq LM3310 19 20 pgnd re ce vgh shdn fb
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 pin descriptions (continued) pin name function 22 ce connect capacitor from this pin to agnd. 23 re connect a resistor between re and pgnd. 24 vgh gpm power supply input. vgh range is 5v to 30v. dap die attach pad. internally connected to gnd. connect agnd and pgnd pins directly to this pad beneath the device. block diagrams figure 2. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: LM3310 boost converter + - + - + - + - r s q current sense osc + - softstart bandgap + - bg ref d ref v in bg t ref bg pwm comp eamp llcomp dcomp driver n1 uvp comp tsd comp reset uvp ref 20 15 21 18 19 350 k : 17 v in 16 14 pgnd 10 agnd agnd pgnd shdn fb v c v in freq sw ss i ss v in
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com figure 3. figure 4. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 4 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310 + - 10 agnd 7 6 9 8 out pos neg av in reset op-amp + - x bg + - reset bg agnd agnd pgnd 10 agnd agnd 21 pgnd pgnd 24 2 23 4 22 3 5 v dd vgh vghm re vdpm ce vflk pgnd pgnd 350 k : 350 k : 1 k : 9r r agnd c e p2 p3 n2 n3 agnd 2x or 3x charge pump pgnd r1 r2 r e v in i ce gpm block
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 absolute maximum ratings (1) (2) v in 7.5v sw voltage 21v fb voltage v in v c voltage (3) 1.265v 0.3v shdn voltage 7.5v freq v in av in 14.5v amplifier inputs/output rail-to-rail vgh voltage 31v vghm voltage vgh vflk, vdpm, v dd voltage 7.5v ce voltage (3) 1.265 + 0.3v re voltage vgh maximum junction temperature 150 c power dissipation (4) internally limited lead temperature 300 c vapor phase (60 sec.) 215 c infrared (15 sec.) 220 c esd susceptibility (5) human body model 2kv (1) absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be ensured. for specifications and test conditions, see the electrical characteristics. (2) if military/aerospace specified devices are required, please contact the texas instruments sales office/ distributors for availability and specifications. (3) under normal operation the v c and ce pins may go to voltages above this value. the maximum rating is for the possibility of a voltage being applied to the pin, however the v c and ce pins should never have a voltage directly applied to them. (4) the maximum allowable power dissipation is a function of the maximum junction temperature, t j (max), the junction-to-ambient thermal resistance, ja , and the ambient temperature, t a . see the electrical characteristics table for the thermal resistance of various layouts. the maximum allowable power dissipation at any ambient temperature is calculated using: p d (max) = (t j(max) ? t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. (5) the human body model is a 100pf capacitor discharged through a 1.5k ? resistor into each pin per jedec standard jesd22-a114. operating conditions operating junction temperature range (1) ? 40 c to +125 c storage temperature ? 65 c to +150 c supply voltage 2.5v to 7v maximum sw voltage 20v vgh voltage range 5v to 30v op-amp supply, av in 4v to 14v (1) all limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). all room temperature limits are 100% production tested. all limits at temperature extremes are specified via correlation using standard statistical quality control (sqc) methods. all limits are used to calculate average outgoing quality level (aoql). copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: LM3310
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com electrical characteristics specifications in standard type face are for t j = 25 c and those with boldface type apply over the full operating temperature range ( t j = ? 40 c to +125 c). unless otherwise specified, v in =2.5v and i l = 0a. parameter test conditions min (1) typ (2) max (1) units i q quiescent current fb = 2v (not switching) 690 1100 a v shdn = 0v 0.5 0.04 8.5 660khz switching 2.1 2.8 ma 1.28mhz switching 3.1 4.0 v fb feedback voltage 1.231 1.263 1.287 v %v fb / v in feedback voltage line 2.5v v in 7v -0.26 0.089 0.42 %/v regulation i cl switch current limit (3) (4) 2.0 2.6 a i b fb pin bias current (5) 27 160 na i ss ss pin current 8.5 11 13.5 a v ss ss pin voltage 1.20 1.24 1.28 v v in input voltage range 2.5 7 v g m error amp transconductance i = 5 a 26 74 133 mho a v error amp voltage gain 69 v/v d max maximum duty cycle f s = 660khz 80 91 % f s = 1.28mhz 80 89 f s switching frequency freq = ground 440 660 760 khz freq = v in 1.0 1.28 1.5 mhz i shdn shutdown pin current v shdn = 2.5v 8 13.5 a v shdn = 0.3v 1 2 i l switch leakage current v sw = 20v 0.03 5 a r dson switch r dson i sw = 500ma 0.18 0.35 ? th shdn shdn threshold output high, v in = 2.5v to 7v 1.4 v output low, v in = 2.5v to 7v 0.4 uvp undervoltage protection on threshold (switch on) 2.5 2.4 v threshold off threshold (switch off) 2.3 2.1 i freq freq pin current freq = v in = 2.5v 2.7 13.5 a operational amplifier v os input offset voltage buffer configuration, v o = 5.7 15 mv av in /2, no load i b input bias current (pos pin) buffer configuration, v o = 200 550 na av in /2, no load (5) v out swing buffer, r l =2k ? , v o min. 0.001 0.03 v buffer, r l =2k ? , v o max. 7.9 7.97 av in supply voltage 4 14 v is+ supply current buffer, v o = av in /2, no load 1.5 7.8 ma i out output current source 90 138 195 ma sink 105 135 175 gate pulse modulation vflk vflk voltage levels rising edge threshold 1.4 v falling edge threshold 0.4 (1) all limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). all room temperature limits are 100% production tested. all limits at temperature extremes are specified via correlation using standard statistical quality control (sqc) methods. all limits are used to calculate average outgoing quality level (aoql). (2) typical numbers are at 25 c and represent the most likely norm. (3) duty cycle affects current limit due to ramp generator. (4) current limit at 0% duty cycle. see typical performance characteristics section for switch current limit vs. v in (5) bias current flows into pin. 6 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 electrical characteristics (continued) specifications in standard type face are for t j = 25 c and those with boldface type apply over the full operating temperature range ( t j = ? 40 c to +125 c). unless otherwise specified, v in =2.5v and i l = 0a. parameter test conditions min (1) typ (2) max (1) units vdpm vdpm voltage levels rising edge threshold 1.4 v falling edge threshold 0.4 v dd(th) v dd threshold vghm = 30v 2.8 3 3.3 v vghm = 5v 0.4 0.5 0.7 i vflk vflk current vflk = 1.5v 4.8 11 a vflk = 0.3v 1.1 2.5 i vdpm vdpm current vdpm = 1.5v 4.8 11 a vdpm = 0.3v 1.1 2.5 i vgh vgh bias current vgh = 30v, vflk high 59 300 a vgh = 30v, vflk low 11 35.5 r vgh-vghm vgh to vghm resistance 20ma current, vgh = 30v 14 28.5 ? r vghm-re vghm to re resistance 20ma current, vgh = vghm 27 55 = 30v r vghm(off) vgh resistance vdpm is low, vghm = 2v 1.2 1.7 k ? i ce ce current ce = 0v 7 11 16 a v ce(th) ce voltage threshold 1.16 1.22 1.34 v copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: LM3310
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com typical performance characteristics shdn pin current ss pin current vs. vs. shdn pin voltage input voltage figure 5. figure 6. freq pin current fb pin current vs. vs. input voltage temperature figure 7. figure 8. ce pin current vdpm pin current vs. vs. input voltage vdpm pin voltage figure 9. figure 10. 8 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310 vdpm pin voltage (v) 0 5 10 15 20 25 vdpm pin current ( p a) 0.5 1.5 2.5 3.5 4.5 5.5 6.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 t j = 25c j t = -40c j t = 125c 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 input voltage (v) ce pin current ( p a) t j = 25c 10.4 10.9 11.4 11.9 12.4 12.9 13.4 t j = -40c t j = 125c fb = 1.265v 0 10 20 30 40 50 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) v = 7.0v in v = 2.5v in fb pin current (na) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 input voltage (v) freq pin current ( p a) t j = 25c 1.5 2.0 2.5 3.0 3.5 4.0 4.5 6.5 7.0 t j = 125c t j = -40c 5.0 5.5 6.0 shdn pin voltage (v) 0 5 10 15 20 30 shdn pin current ( p a) 0.5 1.5 2.5 3.5 4.5 5.5 6.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 t j = 25c j t = -40c t = 125c j 25 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 input voltage (v) t j = 25c t j = -40c t j = 125c ss pin current ( p a) 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 12.0
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 typical performance characteristics (continued) vflk pin current 660khz switching quiescent current vs. vs. vflk pin voltage input voltage figure 11. figure 12. 1.28mhz switching quiescent current 660khz switching quiescent current vs. vs. input voltage temperature figure 13. figure 14. 1.28mhz switching quiescent current 660khz switching frequency vs. vs. temperature temperature figure 15. figure 16. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: LM3310 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature ( o c) 550 560 570 580 590 600 610 switching frequency (khz) -40 v in = 2.5v v in = 7.0v 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) switching i q (ma) v = 2.5v in v = 7.0v in -25 -10 5 20 35 50 65 80 95 110 125 junction temperature ( o c) 1.8 2.2 2.6 3.0 3.4 3.8 4.2 switching i q (ma) -40 v in = 2.5v 2.0 2.4 2.8 3.2 3.6 4.0 v in = 7.0v 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 input voltage (v) switching i q (ma) t j = 25c 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 6.75 t j = -40c t j = 125c 2.5 7.0 1.8 2.0 2.4 2.8 3.0 3.2 3.6 3.8 4.0 switching i q (ma) input voltage (v) 2.2 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 3.4 2.6 t j = 125 o c t j = -40 o c t j = 25 o c vflk pin voltage (v) 0 5 10 15 20 25 vflk pin current ( p a) 0.5 1.5 2.5 3.5 4.5 5.5 6.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 t j = 25c j t = -40c j t = 125c
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com typical performance characteristics (continued) 1.28mhz switching frequency switch current limit vs. vs. temperature input voltage figure 17. figure 18. non-switching quiescent current non-switching quiescent current vs. vs. input voltage input voltage gpm disabled gpm enabled figure 19. figure 20. non-switching quiescent current non-switching quiescent current vs. vs. temperature temperature gpm disabled gpm enabled figure 21. figure 22. 10 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310 junction temperature (c) non-switching i q (ma) 0.66 0.69 0.72 0.75 0.78 0.81 0.84 -40 -25 -10 5 20 35 50 65 80 95 110 125 v in = 7.0v v in = 2.5v gpm disabled junction temperature (c) non-switching i q (ma) 0.93 0.99 1.02 1.08 1.14 1.23 -40 -25 -10 5 20 35 50 65 80 95 110 125 gpm enabled v in = 7.0v v in = 2.5v 0.96 1.05 1.11 1.17 1.20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 input voltage (v) non-switching i q (ma) 0.66 0.69 0.72 0.75 0.78 0.81 0.84 j = -40c t j = 25c t j = 125c t gpm disabled 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 input voltage (v) non-switching i q (ma) 0.93 0.96 1.02 1.05 1.11 1.14 1.20 j = 125c t j = 25c t j = -40c t 0.99 1.08 1.17 gpm enabled 3.3 3.9 4.5 5.1 5.7 6.3 6.9 input voltage (v) 2.12 2.14 2.16 2.18 2.2 2.22 2.24 2.26 2.28 2.3 2.32 switch current limit (a) 2.7 v out = 8v v out = 10v 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) switching frequency (mhz) v = 2.5v in v = 7.0v in
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 typical performance characteristics (continued) power nmos r dson 660khz max. duty cycle vs. vs. input voltage input voltage figure 23. figure 24. 1.28mhz max. duty cycle 660khz max. duty cycle vs. vs. input voltage temperature figure 25. figure 26. 1.28mhz max. duty cycle vs. temperature 1.28mhz application efficiency figure 27. figure 28. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: LM3310 65 70 75 80 85 90 95 0.01 0.10 1.00 load current (a) efficiency (%) v out = 8.5v v in = 5.5v v in = 3.3v v in = 2.5v v in = 4.2v junction temperature (c) maximum duty cycle (%) 89.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 v in = 7.0v v in = 2.5v 89.5 90.0 91.0 92.0 93.5 90.5 91.5 92.5 93.0 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature ( o c) 90.5 93.0 maximum duty cycle (%) -40 92.5 92.0 91.5 91.0 v in = 7.0v v in = 2.5v 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 input voltage (v) maximum duty cycle (%) j = -40c t 89.0 90.0 90.5 91.5 92.5 94.0 89.5 91.0 92.0 93.0 93.5 j = 25c t j = 125c t 90.5 91.0 91.5 92.0 92.5 93.0 input voltage (v) maximum duty cycle (%) 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 t j = 25 o c t j = 125 o c t j = -40 o c 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 input voltage (v) power nmos r dson ( : ) 0.09 0.11 0.13 0.15 0.17 0.19 0.21 0.23 0.25 t a = 100c t a = 25c t a = -40c i sw = 1a
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com typical performance characteristics (continued) vgh pin bias current vs. 1.28mhz application efficiency vgh pin voltage figure 29. figure 30. vgh pin bias current vgh-vghm pmos r dson vs. vs. vgh pin voltage vgh pin voltage figure 31. figure 32. vghm-re pmos r dson vghm off resistance vs. vs. vghm pin voltage temperature figure 33. figure 34. 12 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) 1150 1200 1250 1300 1350 1400 1450 v in =2.5v vghm off resistance ( : ) 5 8 10 13 15 18 20 23 25 28 30 vghm pin voltage (v) 18 23 28 33 38 43 48 gpm pmos 3 r dson ( : ) j = 125c t j = 25c t j = -40c t vgh=vghm i re = 20 ma 0 4 8 12 16 20 24 28 32 vgh pin voltage (v) 0 10 20 30 40 50 60 70 80 vgh pin current ( p a) vflk = high t j = 125c t j = -40c t j = 25c 4 8 12 16 20 24 28 32 vgh pin voltage (v) 10 12 14 16 18 20 22 24 26 28 gpm pmos 2 r dson ( : ) i vghm = 20 ma t j = 125c t j = 25c t j = -40c 0 4 8 12 16 20 24 28 32 vgh pin voltage (v) 0 2 4 6 8 10 12 14 16 vgh pin current ( p a) vflk = low t j = 125c t j = -40c t j = 25c 65 70 75 80 85 90 95 0.01 0.10 1.00 load current (a) efficiency (%) v out = 10.5v v in = 4.2v v in = 3.0v v in = 5.0v
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 typical performance characteristics (continued) op-amp source current op-amp sink current vs. vs. av in av in figure 35. figure 36. op-amp quiescent current op-amp offset voltage vs. vs. av in av in (no load) figure 37. figure 38. op-amp offset voltage vs. load current 1.28mhz, 8.5v application boost load step v out = 8.5v, v in = 3.3v, c out = 20 f 1) v out , 200mv/div, ac 3) i load , 200ma/div, dc t = 200 s/div figure 39. figure 40. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: LM3310 0 20 40 60 80 100 120 -10 10 70 90 110 170 190 210 out - pos (mv) op-amp load current (ma) 140 150 130 30 50 av in = 12v unity gain, pos = av in /2 av in = 8v av in = 4v 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 op-amp i q ( ma) 4 5 6 7 8 9 10 11 12 op-amp input voltage (v) t j = 125 o c unity gain, pos = av in /2 t j = 25 o c t j = -40 o c -5.7 -5.6 -5.5 -5.4 -5.3 -5.2 -5.1 -5.0 -4.9 -4.8 out - pos ( mv) 4 5 6 7 8 9 10 11 12 op-amp input voltage (v) t j = 125 o c unity gain, pos = av in /2 t j = 25 o c t j = -40 o c 4 5 6 7 8 9 10 11 12 op-amp input voltage (v) 100 110 120 130 140 150 160 170 op-amp source current (ma) pos-neg = 0.2v t a = 125 o c t a = 25 o c t a = -40 o c 4 5 6 7 8 9 10 11 12 op-amp input voltage (v) 100 110 120 130 140 150 160 op-amp sink current (ma) neg-pos = 0.2v t a = 125 o c t a = -40 o c t a = 25 o c
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com typical performance characteristics (continued) 1.28mhz, 8.5v application boost startup waveform 1.28mhz, 8.5v application boost startup waveform v out = 8.5v, v in = 3.3v, c out = 20 f, r load = 20 ? , c ss = 100nf v out = 8.5v, v in = 3.3v, c out = 20 f, r load = 20 ? , c ss = 10nf 1) v shdn , 2v/div, dc 1) v shdn , 2v/div, dc 2) v out , 5v/div, dc 2) v out , 5v/div, dc 3) i in , 500ma/div, dc 3) i in , 500ma/div, dc t = 1ms/div t = 200 s/div figure 41. figure 42. 1.28mhz, 8.5v application boost startup waveform v out = 8.5v, v in = 3.3v, c out = 20 f, r load = 20 ? , c ss = open 1) v shdn , 2v/div, dc 2) v out , 5v/div, dc 3) i in , 1a/div, dc t = 40 s/div figure 43. 14 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 operation (a) first cycle of operation (b) second cycle of operation figure 44. simplified boost converter diagram continuous conduction mode the LM3310 contains a current-mode, pwm boost regulator. a boost regulator steps the input voltage up to a higher output voltage. in continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator operates in two cycles. in the first cycle of operation, shown in figure 44 (a), the transistor is closed and the diode is reverse biased. energy is collected in the inductor and the load current is supplied by c out . the second cycle is shown in figure 44 (b). during this cycle, the transistor is open and the diode is forward biased. the energy stored in the inductor is transferred to the load and output capacitor. the ratio of these two cycles determines the output voltage. the output voltage is defined approximately as: where ? d is the duty cycle of the switch ? d and d will be required for design calculations (1) setting the output voltage (boost converter) the output voltage is set using the feedback pin and a resistor divider connected to the output as shown in the typical application circuit . the feedback pin voltage is 1.263v, so the ratio of the feedback resistors sets the output voltage according to the following equation: (2) copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: LM3310 : r fb1 = r fb2 x v out - 1.263 1.263 v out = v in 1-d , d' = (1-d) = v in v out v in c out pwm l r load v in l c out r load x v in l c out r load cycle 1 cycle 2 (a) (b) + v out - + v out - d
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com soft-start capacitor the LM3310 has a soft-start pin that can be used to limit the inductor inrush current on start-up. the external ss pin is used to tailor the soft-start for a specific application but is not required for all applications and can be left open when not needed. when used a current source charges the external soft-start capacitor c ss until it reaches its typical clamp voltage, v ss . the soft-start time can be estimated as: t ss = c ss *v ss /i ss (3) thermal shutdown the LM3310 includes thermal shutdown. if the die temperature reaches 145 c the device will shut down until it cools to a safe temperature at which point the device will resume operation. if the adverse condition that is heating the device is not removed (ambient temperature too high, short circuit conditions, etc...) the device will continue to cycle on and off to keep the die temperature below 145 c. the thermal shutdown has approximately 20 c of hysteresis. when in thermal shutdown the boost regulator, op-amp, and gpm blocks will all be disabled. input under-voltage protection the LM3310 includes input under-voltage protection (uvp). the purpose of the uvp is to protect the device both during start-up and during normal operation from trying to operate with insufficient input voltage. during start-up using a ramping input voltage the uvp circuitry ensures that the device does not begin switching until the input voltage reaches the uvp on threshold. if the input voltage is present and the shutdown pin is pulled high the uvp circuitry will prevent the device from switching if the input voltage present is lower than the uvp on threshold. during normal operation the uvp circuitry will disable the device if the input voltage falls below the uvp off threshold for any reason. in this case the device will not turn back on until the uvp on threshold voltage is exceeded. operational amplifier compensation: the architecture used for the amplifier in the LM3310 requires external compensation on the output. depending on the equivalent resistive and capacitive distributed load of the tft-lcd panel, external components at the amplifier outputs may or may not be necessary. if the capacitance presented by the load is equal to or greater than an equivalent distibutive load of 50 ? in series with 4.7nf no external components are needed as the tft- lcd panel will act as compensation itself. distributed resistive and capacitive loads enhance stability and increase performance of the amplifiers. if the capacitance and resistance presented by the load is less than 50 ? in series with 4.7nf, external components will be required as the load itself will not ensure stability. no external compensation in this case will lead to oscillation of the amplifier and an increase in power consumption. a good choice for compensation in this case is to add a 50 ? in series with a 4.7nf capacitor from the output of the amplifier to ground. this allows for driving zero to infinite capacitance loads with no oscillations, minimal overshoot, and a higher slew rate than using a single large capacitor. the high phase margin created by the external compensation will ensure stability and good performance for all conditions. layout and filtering considerations: when the power supply for the amplifiers (av in ) is connected to the output of the switching regulator, the output ripple of the regulator will produce ripple at the output of the amplifiers. this can be minimized by directly bypassing the av in pin to ground with a low esr ceramic capacitor. for best noise reduction a resistor on the order of 5 ? to 20 ? from the supply being used to the av in pin will create and rc filter and give you a cleaner supply to the amplifier. the bypass capacitor should be placed as close to the av in pin as possible and connected directly to the agnd plane. for best noise immunity all bias and feedback resistors should be in the low k ? range due to the high input impedance of the amplifier. it is good practice to use a small capacitance at the high impedance input terminals as well to reduce noise susceptibility. all resistors and capacitors should be placed as close to the input pins as possible. special care should also be taken in routing of the pcb traces. all traces should be as short and direct as possible. the output pin trace must never be routed near any trace going to the positive input. if this happens cross talk from the output trace to the positive input trace will cause the circuit to oscillate. 16 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 the op-amp is not a three terminal device it has 5 terminals: positive voltage power pin, agnd, positive input, negative input, and the output. the op-amp "routes" current from the power input pin and agnd to the output pin. so in effect an opamp has not two inputs but four, all of which must be kept noise free relative to the external circuits which are being driven by the op-amp. the current from the power pins goes through the output pin and into the load and feedback loop. the current exiting the load and feedback loops then must have a return path back to the op-amp power supply pins. ideally this return path must follow the same path as the output pin trace to the load. any deviation that makes the loop area larger between the output current path and the return current path adds to the probability of noise pick up. gate pulse modulation the gate pulse modulation (gpm) block is designed to provide a modulated voltage to the gate driver circuitry of a tft lcd display. operation is best understood by referring to the gpm block diagram in the block diagrams section, the drawing in figure 45 and the transient waveforms in figure 46 and figure 47 . there are two control signals in the gpm block, vdpm and vflk. vdpm is the enable pin for the gpm block. if vdpm is high, the gpm block is active and will respond to the vflk drive signal from the timing controller. however, if vdpm is low, the gpm block will be disabled and both pmos switches p2 and p3 will be turned off. the vghm node will be discharged through a 1k ? resistor and the nmos switch n2. when vdpm is high, typical waveforms for the gpm block can be seen in figure 45 . the pin vgh is typically driven by a 2x or 3x charge pump. in most cases, the 2x or 3x charge pump is a discrete solution driven from the sw pin and the output of the boost switching regulator. when vflk is high, the pmos switch p2 is turned on and the pmos switch p3 is turned off. with p2 on, the vghm pin is pulled to the same voltage applied to the vgh pin. this provides a high gate drive voltage, vghm max , and can source current to the gate drive circuitry. when vflk is high, nmos switch n3 is on which discharges the capacitor ce. figure 45. when vflk is low, the nmos switch n3 is turned off which allows current to charge the c e capacitor. this creates a delay, t delay , given by the following equations: t delay ? 1.265v(c e + 7pf)/i ce (4) when the voltage on ce reaches about 1.265v and the vflk signal is low, the pmos switch p2 will turn off and the pmos switch p3 will turn on connecting resistor r3 to the vghm pin through p3. this will discharge the voltage at vghm at some rate determined by r3 creating a slope, m r , as shown in figure 45 . the vghm pin is no longer a current source, it is now sinking current from the gate drive circuitry. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: LM3310 vghm max vghm min m r ~1.94v 0 0 0 tt t vghm vflk ce ~1.265v t delay
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com as vghm is discharged through r3, the comparator connected to the pin v dd monitors the vghm voltage. pmos switch p3 will turn off when the following is true: vghm min ? 10v x r2/(r1 + r2) where ? v x is some voltage connected to the resistor divider on pin v dd (5) v x is typically connected to the output of the boost switching regulator. when pmos switch p3 turns off, vghm will be high impedance until the vflk pin is high again. figure 46 and figure 47 give typical transient waveforms for the gpm block. waveform (1) is the vghm pin, (2) is the vflk and (3) is the vdpm. the output of the boost switching regulator is operating at 8.5v and there is a 3x discrete charge pump (~23.5v) supplying the vgh pin. in figure 46 and figure 47 , the vghm pin is driving a purely capacitive load, 4.7nf. the value of resistor r1 is 15kohm, r2 is 1.1k ? and r3 is 750 ? . in both transient plots, there is no c e delay capacitor. figure 46. waveform figure 47. waveform in the gpm block diagram, a signal called ? reset ? is shown. this signal is generated from the v in under-voltage lockout, thermal shutdown, or the shdn pin. if the v in supply voltage drops below 2.3v, typically, then the gpm block will be disabled and the vghm pin will discharge through nmos switch n2 and the 1k ? resistor. this applies also if the junction temperature of the device exceeds 145 c or if the shdn signal is low. as shown in the block diagrams , both vdpm and vflk have internal 350k ? pull down resistors. this puts both vdpm and vflk in normally ? off ? states. typical vdpm and vflk pin currents can be found in the typical performance characteristics section. 18 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 introduction to compensation (boost converter) (a) inductor current (b) diode current figure 48. the LM3310 is a current mode pwm boost converter. the signal flow of this control scheme has two feedback loops, one that senses switch current and one that senses output voltage. to keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet certain criteria. the inductor, along with input and output voltage, will determine the slope of the current through the inductor (see figure 48 (a)). if the slope of the inductor current is too great, the circuit will be unstable above duty cycles of 50%. a 10 h inductor is recommended for most 660 khz applications, while a 4.7 h inductor may be used for most 1.28 mhz applications. if the duty cycle is approaching the maximum of 85%, it may be necessary to increase the inductance by as much as 2x. see inductor and diode selection for more detailed inductor sizing. the LM3310 provides a compensation pin (v c ) to customize the voltage loop feedback. it is recommended that a series combination of r c and c c be used for the compensation network, as shown in the typical application circuit . for any given application, there exists a unique combination of r c and c c that will optimize the performance of the LM3310 circuit in terms of its transient response. the series combination of r c and c c introduces a pole-zero pair according to the following equations: (6) copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links: LM3310 hz 1 2 s (r c + r o )c c f pc = hz 1 f zc = 2 s r c c c t (s) t (s) l i ' i l_avg i d_avg =i out_avg d*ts ts d*ts ts i l (a) i d (a) l v in l v v out in l v v out in (a) (b)
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com where ? r o is the output impedance of the error amplifier, approximately 900k ? (7) for most applications, performance can be optimized by choosing values within the range 5k ? r c 100k ? (r c can be up to 200k ? if c c2 is used, see high output capacitor esr compensation ) and 68pf c c 4.7nf. refer to the application information section for recommended values for specific circuits and conditions. refer to the compensation section for other design requirement. compensation this section will present a general design procedure to help insure a stable and operational circuit. the designs in this datasheet are optimized for particular requirements. if different conversions are required, some of the components may need to be changed to ensure stability. below is a set of general guidelines in designing a stable circuit for continuous conduction operation, in most all cases this will provide for stability during discontinuous operation as well. the power components and their effects will be determined first, then the compensation components will be chosen to produce stability. inductor and diode selection although the inductor sizes mentioned earlier are fine for most applications, a more exact value can be calculated. to ensure stability at duty cycles above 50%, the inductor must have some minimum value determined by the minimum input voltage and the maximum output voltage. this equation is: where ? fs is the switching frequency ? d is the duty cycle ? r dson is the on resistance of the internal switch taken from the graph "r dson vs. v in " in the typical performance characteristics section (8) this equation is only good for duty cycles greater than 50% (d > 0.5), for duty cycles less than 50% the recommended values may be used. the value given by this equation is the inductance necessary to supress sub-harmonic oscillations. in some cases the value given by this equation may be too small for a given application. in this case the average inductor current and the inductor current ripple must be considered. the corresponding inductor current ripple, average inductor current, and peak inductor current as shown in figure 48 (a) is given by: (9) (10) (11) continuous conduction mode occurs when i l is less than the average inductor current and discontinuous conduction mode occurs when i l is greater than the average inductor current. care must be taken to make sure that the switch will not reach its current limit during normal operation. the inductor must also be sized accordingly. it should have a saturation current rating higher than the peak inductor current expected. the output voltage ripple is also affected by the total ripple current. the output diode for a boost regulator must be chosen correctly depending on the output voltage and the output current. the typical current waveform for the diode in continuous conduction mode is shown in figure 48 (b). the diode must be rated for a reverse voltage equal to or greater than the output voltage used. the average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current. during short circuit testing, or if short circuit conditions are possible in the application, the diode current rating must exceed the switch current limit. using schottky diodes with lower forward voltage drop will decrease power dissipation and increase efficiency. 20 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310 i l(ave) + ' i l i l(peak) | i out k d' i l(ave) | ' i l = (in amps) v in d 2lfs v in r dson 0.144 fs l > d d' - 1 (in h)
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 dc gain and open-loop gain since the control stage of the converter forms a complete feedback loop with the power components, it forms a closed-loop system that must be stabilized to avoid positive feedback and instability. a value for open-loop dc gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover frequency and the phase margin. a high phase margin (greater than 45 ) is desired for the best stability and transient response. for the purpose of stabilizing the LM3310, choosing a crossover point well below where the right half plane zero is located will ensure sufficient phase margin. to ensure a bandwidth of ? or less of the frequency of the rhp zero, calculate the open-loop dc gain, a dc . after this value is known, you can calculate the crossover visually by placing a ? 20db/decade slope at each pole, and a +20db/decade slope for each zero. the point at which the gain plot crosses unity gain, or 0db, is the crossover frequency. if the crossover frequency is less than ? the rhp zero, the phase margin should be high enough for stability. the phase margin can also be improved by adding c c2 as discussed later in this section. the equation for a dc is given below with additional equations required for the calculation: where ? r l is the minimum load resistance ? g m is the error amplifier transconductance found in the electrical characteristics table (12) (13) (14) (15) mc ? 0.072fs (in v/s) (16) where ? v in is the minimum input voltage ? r dson is the value chosen from the graph "nmos r dson vs. input voltage" in the typical performance characteristics section (17) input and output capacitor selection the switching action of a boost regulator causes a triangular voltage waveform at the input. a capacitor is required to reduce the input ripple and noise for proper operation of the regulator. the size used is dependant on the application and board layout. if the regulator will be loaded uniformly, with very little load changes, and at lower current outputs, the input capacitor size can often be reduced. the size can also be reduced if the input of the regulator is very close to the source output. the size will generally need to be larger for applications where the regulator is supplying nearly the maximum rated output or if large load steps are expected. a minimum value of 10 f should be used for the less stressful condtions while a 22 f to 47 f capacitor may be required for higher power and dynamic loads. larger values and/or lower esr may be needed if the application requires very low ripple on the input source voltage. the choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output voltage ripple. it is recommended that low esr (equivalent series resistance, denoted r esr ) capacitors be used such as ceramic, polymer electrolytic, or low esr tantalum. higher esr capacitors may be used but will require more compensation which will be explained later on in the section. the esr is also important because it determines the peak to peak output voltage ripple according to the approximate equation: v out ? 2 i l r esr (in volts) (18) a minimum value of 10 f is recommended and may be increased to a larger value. after choosing the output capacitor you can determine a pole-zero pair introduced into the control loop by the following equations: copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links: LM3310 f p1 = 1 2 s (r esr + r l )c out (in hz) m1 # v in r dson l (in v/s) n = 1+ 2mc m1 (no unit) leff = l (d') 2 z c (in rad/s) 2fs nd' # a dc(db) = 20log 10 {[( z cleff)// r l ]//r l } (in db) r fb1 + r fb2 r fb2 ( ) g m r o d' r dson
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com where ? r l is the minimum load resistance corresponding to the maximum load current (19) (20) the zero created by the esr of the output capacitor is generally very high frequency if the esr is small. if low esr capacitors are used it can be neglected. if higher esr capacitors are used see the high output capacitor esr compensation section. some suitable capacitor vendors include vishay, taiyo-yuden, and tdk. right half plane zero a current mode control boost regulator has an inherent right half plane zero (rhp zero). this zero has the effect of a zero in the gain plot, causing an imposed +20db/decade on the rolloff, but has the effect of a pole in the phase, subtracting another 90 in the phase plot. this can cause undesirable effects if the control loop is influenced by this zero. to ensure the rhp zero does not cause instability issues, the control loop should be designed to have a bandwidth of less than ? the frequency of the rhp zero. this zero occurs at a frequency of: where ? i load is the maximum load current (21) selecting the compensation components the first step in selecting the compensation components r c and c c is to set a dominant low frequency pole in the control loop. simply choose values for r c and c c within the ranges given in the introduction to compensation section to set this pole in the area of 10hz to 500hz. the frequency of the pole created is determined by the equation: where ? r o is the output impedance of the error amplifier, approximately 900k ? (22) since r c is generally much less than r o , it does not have much effect on the above equation and can be neglected until a value is chosen to set the zero f zc . f zc is created to cancel out the pole created by the output capacitor, f p1 . the output capacitor pole will shift with different load currents as shown by the equation, so setting the zero is not exact. determine the range of f p1 over the expected loads and then set the zero f zc to a point approximately in the middle. the frequency of this zero is determined by: (23) now r c can be chosen with the selected value for c c . check to make sure that the pole f pc is still in the 10hz to 500hz range, change each value slightly if needed to ensure both component values are in the recommended range. high output capacitor esr compensation when using an output capacitor with a high esr value, or just to improve the overall phase margin of the control loop, another pole may be introduced to cancel the zero created by the esr. this is accomplished by adding another capacitor, c c2 , directly from the compensation pin v c to ground, in parallel with the series combination of r c and c c . the pole should be placed at the same frequency as f z1 , the esr zero. the equation for this pole follows: (24) to ensure this equation is valid, and that c c2 can be used without negatively impacting the effects of r c and c c , f pc2 must be greater than 10f zc . 22 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310 f pc2 = 1 2 s c c2 (r c //r o ) (in hz) f zc = 1 2 s c c r c (in hz) f pc = 1 2 s (r c + r o )c c (in hz) (in hz) rhpzero = v out (d') 2 2 s, load l f z1 = 1 2 s r esr c out (in hz)
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 checking the design with all the poles and zeros calculated the crossover frequency can be checked as described in the section dc gain and open-loop gain . the compensation values can be changed a little more to optimize performance if desired. this is best done in the lab on a bench, checking the load step response with different values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. this should produce a stable, high performance circuit. for improved transient response, higher values of r c should be chosen. this will improve the overall bandwidth which makes the regulator respond more quickly to transients. if more detail is required, or the most optimum performance is desired, refer to a more in depth discussion of compensating current mode dc/dc switching regulators. power dissipation the output power of the LM3310 is limited by its maximum power dissipation. the maximum power dissipation is determined by the formula p d = (t jmax - t a )/ ja where ? t jmax is the maximum specified junction temperature (125 c) ? t a is the ambient temperature ? ja is the thermal resistance of the package (25) layout considerations the input bypass capacitor c in , as shown in the typical application circuit , must be placed close to the ic. this will reduce copper trace resistance which effects input voltage ripple of the ic. for additional input voltage filtering, a 100nf bypass capacitor can be placed in parallel with c in , close to the v in pin, to shunt any high frequency noise to ground. the output capacitor, c out , should also be placed close to the ic. any copper trace connections for the c out capacitor can increase the series resistance, which directly effects output voltage ripple. the feedback network, resistors r fb1 and r fb2 , should be kept close to the fb pin, and away from the inductor, to minimize copper trace connections that can inject noise into the system. r e and c e should also be close to the re and ce pins to minimize noise in the gpm circuitry. trace connections made to the inductor and schottky diode should be minimized to reduce power dissipation and increase overall efficiency. for more detail on switching power supply layout considerations see application note an-1149 : layout guidelines for switching power supplies . for op-amp layout please refer to the operational amplifier section. figure 49 , figure 50 , and figure 51 in the application information section following show the schematic and an example of a good layout as used in the LM3310/11 evaluation board. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 23 product folder links: LM3310
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com application information figure 49. evaluation board schematic figure 50. evaluation board layout (top layer) 24 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310 v dd cin cin1 cout cout1 cout2 v in fb sw ss agnd pos neg shdn freq LM3310 v c dcp1 d1 l1 rfb1 v in pgnd out vdpm vghm vflk ce re vgh re ce av in ccp1 rvdd1 rvdd2 voutx2 rfb2 css cc1 rc1 cc2 vout ccp2 dcp2 ccp3 voutx3 ccp4 ccp5 dcp3 -vout cg1 cg2 pos rc6 rc7 co2 neg rac2 cac2 cac1 rac1 out vflk vdpm vghm vgh co1
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 figure 51. evaluation board layout (bottom layer) figure 52. li-ion to 8v, 1.28mhz application copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 25 product folder links: LM3310 v dd c ss c in c out v in fb sw ss agnd pos neg shdn freq LM3310 v c d 3 d 2 d 1 l r fb1 160k v in c c r c pgnd out vdpm vghm vflk ce re vgh r e c e = 15v av in c3 c4 r1 r2 v out v oh 22 p f 2 x 10 p f ceramic r fb2 30k 10 p h 2.4k 33 pf 13k 1.2k 10 nf 1 nf 30k 1 p f 1 p f = 8v = 2.9v - 4.2v connect to vgh 68 pf c c2
LM3310 snvs341e ? august 2005 ? revised may 2013 www.ti.com figure 53. 5v to 10.5v, 1.28mhz application table 1. some recommended inductors (others may be used) manufacturer inductor contact information coilcraft do3316 and dt3316 series www.coilcraft.com 800-3222645 tdk slf10145 series www.component.tdk.com 847-803-6100 pulse p0751 and p0762 series www.pulseeng.com sumida cdrh8d28 and cdrh8d43 series www.sumida.com table 2. some recommended input and output capacitors (others may be used) manufacturer capacitor contact information vishay sprague 293d, 592d, and 595d series tantalum www.vishay.com 407-324-4140 taiyo yuden high capacitance mlcc ceramic www.t-yuden.com 408-573-4150 esrd seriec polymer aluminum electrolytic cornell dubilier www.cde.com spv and afk series v-chip series high capacitance mlcc ceramic panasonic www.panasonic.com eej-l series tantalum 26 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: LM3310 v dd c ss c in c out v in fb sw ss agnd pos neg shdn freq LM3310 v c d 3 d 2 d 1 l r fb1 16k v in c c r c pgnd out vdpm vghm vflk ce re vgh r e c e = 20v av in c3 c4 r1 r2 v out v oh 22 p f 4 x 10 p f ceramic r fb2 2.2k 10 p h 2.4k 33 pf 13k 1.2k 10 nf 100 pf 33k c ff 33 pf 1 p f 1 p f = 10.5v = 5v connect to vgh
LM3310 www.ti.com snvs341e ? august 2005 ? revised may 2013 revision history changes from revision d (may 2013) to revision e page ? changed layout of national data sheet to ti format .......................................................................................................... 26 copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 27 product folder links: LM3310
package option addendum www.ti.com 8-oct-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples LM3310sq/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l3310sq (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 8-oct-2015 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant LM3310sq/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 package materials information www.ti.com 2-sep-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) LM3310sq/nopb wqfn rtw 24 1000 210.0 185.0 35.0 package materials information www.ti.com 2-sep-2015 pack materials-page 2
mechanical da t a r tw0024a www .ti.com s q a 2 4 a ( r e v b )
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2015, texas instruments incorporated

▲Up To Search▲

Price & Availability of LM3310

	To Download LM3310 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .